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71M6545/71M6545H Data Sheet
Name
Location
Rst Wk Dir
Description
FIR_LEN[1:0]
210C[2:1]
0
0
R/W
Determines the number of ADC cycles in the ADC decimation FIR filter.
PLL_FAST = 1:
FIR_LEN[1:0] ADC Cycles
00 141
01 288
10 384
PLL_FAST = 0:
FIR_LEN[1:0] ADC Cycles
00 135
01 276
10 Not Allowed
The ADC LSB size and full-scale values depend on the FIR_LEN[1:0] setting. Refer to
Table 73 on page 106 and Table 91 on page 121 for details.
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or the Flash Page
Erase cycle. Specific patterns are expected for FLSH_ERASE in order to initiate the
appropriate Erase cycle. (default = 0x00).
FLSH_ERASE[7:0]
SFR 94[7:0]
0
0
W
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to
FLSH_PGADR[6:0] ( SFR 0xB7 ).
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to
FLSH_MEEN ( SFR 0xB2 ) and the debug (CC) port must be enabled.
Any other pattern written to FLSH_ERASE has no effect.
FLSH_MEEN
FLSH_PEND
FLSH_PGADR[6:0]
FLSH_PSTWR
SFR B2[1]
SFR B2[3]
SFR B7[7:1]
SFR B2[2]
0
0
0
0
0
0
0
0
W
R
W
R/W
Mass Erase Enable
0 = Mass Erase disabled (default).
1 = Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Indicates that a posted flash write is pending. If another flash write is attempted, it is
ignored.
Flash Page Erase Address
Flash Page Address (page 0 thru 63) that is erased during the Page Erase cycle.
(default = 0x00).
Must be re-written for each new Page Erase cycle.
Enables posted flash writes. When 1, and if CE_E = 1, flash write requests are stored
in a one element deep FIFO and are executed when CE_BUSY falls. FLSH_PEND can
be read to determine the status of the FIFO. If FLSH_PSTWR = 0 or if CE_E = 0, flash
writes are immediate.
v2
91
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